The MC68302 is a versatile one-chip processor that incorporates the main building blocks needed for the design of a wide variety of networking and communications products.
The MC68302 was the first device to offer the benefits of a closely coupled, industry-standard, MC68000/MC68008 microprocessor core and a flexible communications architecture. This multi-channel communications device may be configured to support a number of popular industry-standard interfaces, including those for the Integrated Services Digital Network (ISDN) basic rate and terminal adapter applications. Through a combination of architectural and programmable features, concurrent operation of different protocols is easily achieved using the MC68302. Data concentrators, modems, line cards, bridges, and gateways are examples of other suitable applications for this versatile device.
The MC68302 is an HCMOS device consisting of an MC68000/MC68008 microprocessor core, a system integration block (SIB), and a communications processor (CP).
This device is still recommended for new designs.
Features
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MC68000/MC68008 Microprocessor Core
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Efficient architecture involves a separate RISC processor for handling communications
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Three Serial Communications Controllers (SCCs)
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Support for HDLC/SDLC, Bisync, UART, DDCMP, and Totally Transparent protocols.
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Two Serial Management Controllers (SMCs) for IDL and GCI Channel.
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Available at 16, 20, 25, and 33 MHz in three different Thin Quad Flat Pack Packages.
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Strong 3rd Party tools support.
Typical Applications
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ISDN equipment
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Data Concentrators
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Modems
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Line Cards
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Network Bridges
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Gateways
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MC68000/MC68008 Microprocessor Core (May be disabled to use the IMP as a peripheral)
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SIB Including:
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Independent Direct Memory Access (IDMA) Controller
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Interrupt controller with two modes of operation
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Parallel I/O ports, some with interrupt capability
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On-Chip 1152-bytes of dual-port RAM
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Three timers, with a software watchdog timer
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Four programmable chip-select lines with wait-state logic
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Programmable address mapping of dual-port RAM and IMP registers
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On-Chip clock generator with an output clock signal
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System Control
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Bus arbitration logic with low interrupt latency support
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System control register
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Hardware watchdog for monitoring bus activity
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Low power (Standby) modes
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Disable CPU logic (M68000)
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Freeze control for debugging selected on-chip peripherals
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DRAM refresh controller
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CP Including:
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Main controller (RISC Processor)
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Three full-duplex Serial Communication/Controllers with the following protocols:
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HDLC/SDLC
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Bisync
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UART
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DDCMP
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Totally Transparent
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V.110
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Six serial DMA channels dedicated to the three SOCs
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Capability to send/receive up to eight buffers/frames without M68000 core intervention
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Flexible physical interface accessible by SCCs for Inter-chip Digital Link (IDL), General Circuit Interface (GCI).
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Pulse Code Modulation (PCM), and Non-multiplexed Serial Interface (NMSI) Operation.