The MSC7116 device is a highly integrated DSP processor that contains the StarCoreTM SC1400 core, 384 KB of SRAM memory, a 16 KB 16-way Instruction Cache, an 8 KB boot ROM, a 10/100 Mbps MII/RMII Ethernet interface, two 128-channel Time-Division Multiplexing (TDM) interfaces with hardware support for μ/A-law decoding/encoding, a UART, a 32-channel DMA controller, a 16-bit Host Interface (HDI16) to support an external host processor, a programmable interrupt controller (PIC), an I⊃2;C interface, two 16-bit quad cascadable timers, GPIO signals, and OCE10 module and event port for enhanced debug and system integration capability. The SC1400 core has four ALUs and performs at 1000 DSP Million Multiply Accumulates per Second (MMACS) with an internal 266 MHz clock at 1.2 V.
Target Applications
The MSC7116 device targets high-bandwidth highly computational DSP applications and is optimized for Enterprise class packet telephony applications, providing a competitive price per channel for voice-over-packet systems.
View Block Diagram
Features
-
1000 MMACS running at 266 MHz
-
Four 16-bit data ALUs, sixteen 40-bit data registers, and twenty-seven 32-bit address registers
-
Up to six instructions executed per clock cycle
-
Variable-length execution set (VLES) model
-
JTAG port designed to comply with Std 1149.1TM and OCE10 module
-
SC1400 core processor
-
16 KB, 16-way instruction cache (ICache)
-
Programmable instruction fetch unit
-
Write buffer (4-entry)
-
Extended core interface module
-
408 KB total
-
192 KB of M1 memory
-
16 KB ICache
-
192 KB internal shared memory (M2)
-
8 KB boot ROM
-
DDR memory controller
-
Glueless interface to 133 MHz DDR-DRAM
-
14-bit external address bus supporting up to 1 GB of DDR memory
-
16- or 32-bit external data bus
-
Byte enables, atomic operation, and data pipelining
-
Multi-channel DMA controller with up to 32 time-multiplexed channels
-
Priority-based time-multiplexing between channels using 16 internal priority levels
-
Priority can be fixed or round-robin
-
Flexible channel configuration
-
IEEE 802.3, 802.3u, 802.3x, and 802.3ac compliant 10/100 Mbps MII/RMII Ethernet interface
-
Two time-division multiplexing (TDM) modules, each supporting up to 128 channels and glueless interface to E1/T1 frames and MVIP, SCAS, and H.110 buses
-
16-bit host interface (HDI16) with glueless connection to industry-standard microcontrollers, microprocessors, and DSPs
-
Two 16-bit quad timers
-
RS-232 interface/universal asynchronous receiver/transmitter (UART)
-
I⊃2;C interface
-
Up to 37 general-purpose input/output (GPIO) signals