The MPC8533E combines a robust processor core built on Power Architecture® technology, enhanced peripherals and high-speed interconnect technology to balance processor performance with I/O system throughput and achieve clock speeds scaling up to 667 MHz throughput with headroom for 1.0 GHz.
The MPC8533E processor offers a wide range of high-speed connectivity options, including Gigabit Ethernet (GbE) and multiple PCI Express® connections. Support for these high-speed interfaces enables scalable connectivity to network processors and/or ASICs in the data plane while the PowerQUICC III handles complex, computationally demanding control plane processing tasks. The MPC8533 also provides support for legacy PowerQUICC III interfaces such as PCI, I²C, dual universal asynchronous receiver/transmitters (DUART) and local bus connections. These processors also feature a next-generation double data rate (DDR2) memory controller, enhanced GbE support, v2 e500 double precision floating point and the field proven 90 nm PowerQUICC III integrated security engines.
The MPC8533E processor includes 256 KB L2 cache, an integrated security engine, 64-bit DDR and DDR2, 32-bit PCI bus controller, multiple PCI Express interfaces, local bus I/O interfaces and two GbE interfaces. The combination of these features makes this device an optimal communications processing solution for Ethernet-only or PCI Express interworking applications, such as enterprise networking and advanced multifunction printer (MFP) and imaging applications.
The MPC8533E device is ideal for connecting high-speed DDR2 memory interfaces and peripherals in high-performance distributed systems. Examples include control plane processing, protocol processing and other compute-intensive applications requiring high-speed, peer-level communications with a low pin count. The MPC8533E is a full-featured, high-performance processor that is optimized for applications that are power sensitive.
Features
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Embedded e500 core, initial offerings up to 667 MHz, targeting up to 1.0 GHz
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Dual dispatch superscalar, 7-stage pipeline design with out-of-order issue and execution
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2,240 MIPS at 1.0 GHz (estimated Dhrystone 2.1)
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36-bit physical addressing
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Enhanced hardware and software debug support
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Double-precision embedded scalar and vector floating-point APUs
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Memory management unit (MMU)
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Double-precision embedded scalar and vector floating-point APUs
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Integrated L1/L2 cache
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L1 cache—32 KB data and 32 KB instruction cache with line-locking support
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L2 cache—256 KB (8-way set associative); 256/128/64/32 KB can be used as SRAM
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L1 and L2 hardware coherency
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L2 cache and I/O transactions can be stashed into L2 cache regions
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Integrated DDR memory controller with full ECC support, offering:
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200 MHz clock rate (400 MHz data rate), 64-bit, 2.5V/2.6V I/O, DDR SDRAM
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267 MHz clock rate (up to 533 MHz data rate), 64-bit, 1.8V I/O, DDR2 SDRAM
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Integrated security engine supporting DES, 3DES, MD-5, SHA-1/2, AES, RSA, RNG, Kasumi F8/F9 and ARC-4 encryption algorithms
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Two on-chip Three Speed Ethernet controllers (ETSECs) supporting 10 Mbps, 100 Mbps and 1 Gbps Ethernet/IEEE® 802.3 networks with MII, RMII, RGMII, and RTBI physical interfaces:
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TCP/UDP/IP checksum acceleration
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Advanced QoS features
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General-purpose input/output (GPIO)
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PCI Exp