The MSC7118 device is a member of the Freescale MSC711x family, a high-performance, cost-effective family of DSPs based on the StarCore ™ SC1400 core that offers system solutions, flexibility with peripherals and performance, and overall system cost savings. Devices in the MSC711x family target high-bandwidth highly computational DSP applications and are optimized for packet telephony applications, providing a competitive price per channel for voice over packet systems. The MSC7118 is a highly integrated DSP that contains the SC1400 core, on-chip emulation logic, 448 KB of SRAM memory, a 16 KB ICache, an 8 KB boot ROM, an 8 KB trace buffer, a 32-channel DMA controller, a 4-layer crossbar switch, a DDR memory controller, three 128-channel time-division multiplexing (TDM) interfaces with hardware support for m/A-law decoding/encoding, a UART, a 16-bit host interface (HDI16) to support an external host processor, a programmable interrupt controller (PIC), an I2C interface, eight timers, GPIO signals, and a JTAG port. The SC1400 core has four ALUs and performs at 1200 DSP million multiply accumulates per second (MMACS) with an internal 300 MHz clock at 1.2 V.
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Features
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1200 MMACS running at 300 MHz
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Four 16-bit data ALUs, sixteen 40-bit data registers, and twenty-seven 32-bit address registers
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Up to six instructions executed per clock cycle
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Variable-length execution set (VLES) model
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JTAG port designed to comply with Std 1149.1TM and OCE10 emulation module
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SC1400 core processor
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16 KB, 16-way instruction cache (ICache)
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Programmable instruction fetch unit
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Write buffer (4-entry)
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Extended core interface module
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472 KB total
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256 KB of M1 memory
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16 KB ICache
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192 KB internal shared memory (M2)
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8 KB boot ROM
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DDR memory controller
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Glueless interface to 100 MHz DDR-DRAM
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14-bit external address bus supporting up to 1 GB of DDR memory
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16- or 32-bit external data bus
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Byte enables, atomic operation, and data pipelining
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Multi-channel DMA controller with up to 32 time-multiplexed channels
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Priority-based time-multiplexing between channels using 16 internal priority levels
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Priority can be fixed or round-robin
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Flexible channel configuration
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Three time-division multiplexing (TDM) modules, each supporting up to 128 channels and glueless interface to E1/T1 frames and MVIP, SCAS, and H.110 buses
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16-bit host interface (HDI16) with glueless connection to industry-standard microcontrollers, microprocessors, and DSPs
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Two 16-bit quad timers
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RS-232 interface/universal asynchronous receiver/transmitter (UART)
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I⊃2;C interface
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General-purpose input/output (GPIO) signals
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Interrupt controller to handle external interrupt functions (input an