MPC866 PowerQUICC™ Family is a 0.18 micron version of the MPC862 PowerQUICC Family and can operate up to 133 MHz on the MPC8xx core with a 66 MHz external bus. The MPC866 Family has a 1.8 V core and has a 3.3 V I/O operation with 5 V TTL compatibilty. The MPC866 Integrated Communications Controller Family is a versatile one-chip integrated microprocessor and peripheral combination that can be used in a variety of controller applications. It particularly excels in both communications and networking systems.
The MPC866 Family is a a Power Architecture-based derivative of Freescale's Quad Integrated Communications Controller (PowerQUICC). The CPU on the MPC866 is the MPC8xx core, a 32-bit microprocessor built on Power Architecture technology, incorporating memory management units (MMUs) and instruction and data caches. The MPC866P is the superset of this family of devices.
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Features
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Maximum frequency operation of the external bus is 66 MHz
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Single-issue, 32-bit core (compatible with Power Architecture technology) with 32, 32-bit general-purpose registers (GPRs)
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The MPC866 Family provides enhanced ATM functionality as found on the MPC862. The MPC866 adds major new features available in "enhanced SAR" (ESAR) mode, including the following:
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Improved operation, administration and maintenance (OAM) support
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OAM performance monitoring (PM) support
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Multiple APC priority levels available to support a range of traffic pace requirements
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Port-to-port switching capability without the need for RAM-based microcode
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Simultaneous MII (100Base-T) and UTOPIA (half-duplex) capability
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Optional statistical cell counters per PHY
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UTOPIA level 2 compliant interface with added FIFO buffering to reduce the total cell transmission time. (The earlier UTOPIA level 1 specification is also supported.)
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Parameter RAM for both SPI and I2C can be relocated without RAM-based microcode
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Supports full-duplex UTOPIA both master (ATM side) and slave (PHY side) operation using a "split" bus
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AAL2/VBR functionality is ROM-resident
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Up to 32-bit data bus (dynamic bus sizing for 8, 16, and 32 bits)
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32 address lines
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Memory controller (eight banks)
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General-purpose timers
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Fast Ethernet controller (FEC)
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System integration unit (SIU)
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Interrupts
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Communications processor module (CPM)
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Four baud rate generators
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Four SCCs (serial communication controllers)
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Two SMCs (serial management channels)
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One SPI (serial peripheral interface)
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One I2C (inter-integrated circuit) port
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Time-slot assigner (TSA)
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Parallel interface port (PIP)
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PCMCIA interface
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Debug interface
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1.8 V Core and 3.3 V I/O operation with 5-V TTL compatibility
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357-pin ball grid array (BGA) package
Note 1: Where nn = 50, 66, 100, or 133