Introducing the next generation of PowerQUICC II™ processors: the MPC8270, MPC8275 and MPC8280.
Utilizing Freescale's HiPerMOS7 0.13-micron process technology, the next generation PowerQUICC II family offers a range of performance, feature enhancements and package options with lower power requirements. Ideal for wired and wireless infrastructure communications processing tasks, enhancements to the PowerQUICC II family offer system designers a high degree of integrated features and functionality and a compelling, proven architecture.
The next generation of PowerQUICC II processors is an optimum solution for integrated control and forwarding plane processing in high-end communications and networking equipment -- such as routers, DSLAMs, remote access concentrators, telecom switching equipment and cellular base stations. Combining extensive layer 2 functionality with control plane processing, Freescale's PowerQUICC II processors include a high-performance embedded 603e™ core built on Power Architecture technology, and a powerful RISC-based Communications Processor Module (CPM). The CPM off-loads peripheral tasks from the embedded Power Architecture core and provides support for multiple communications protocols including 10/100Mbps Ethernet, 155Mbps ATM and 256 HDLC channels. And, of course, the next generation PowerQUICC II devices retain full software compatibility with the PowerQUICC II family.
A range of performance and package options
Taking advantage of the 0.13-micron process, the next generation of PowerQUICC II devices offers significant performance increases and power savings over the current generation PowerQUICC II devices, with speeds of up to 450MHz and 300MHz in the core and CPM respectively at less than 2 watts. The new processors continue to enhance the PowerQUICC architecture's industry-leading ATM support, offering up to 2 UTOPIA ports with support for up to 31 PHYs per interface -- ideal for high-density DSLAM line cards.
The next generation of PowerQUICC II solutions also delivers support for USB, an on-target addition for high performance SOHO and CPE networking equipment. And unlike most other integrated communications processors in the market, the PowerQUICC architecture integrates two processing cores to handle specific tasks: the core built on Power Architecture technology and the RISC-based CPM -- enabling a balanced approach for systems by handling both high-level tasks and low-level communications all in one integrated device.
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Features
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603e core with 16K inst and 16K data caches
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64-bit 60x bus, 32-bit PCI/local bus
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128K ROM, 32K IRAM, 32K DPRAM
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Three FCCs for 10/100 Ethernet
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128 HDLC channels, 4 TDMs
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4 SCCs, 2 SMCs, SPI, I2C
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Memory controller built from SDRAM, UPM, GPCM machines
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New features -- USB, RMII
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Performance
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266 MHz CPU, 200 MHz CPM, 66 MHz bus
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~ 1W @ full performance, 1.5V
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Technology
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HIP7AP .13 micron, 3.3V I/O, 1.5V Core
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516 PBGA, 27x27mm, 1mm ball pitch
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ZQ package has lead-bearing spheres
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VR package is lead-free
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603e core with 16K inst and 16K data caches
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64-bit 60x bus, 32-bit PCI bus
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128K ROM, 32K IRAM, 32K DPRAM
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Three FCCs for 10/100 Ethernet
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128 HDLC channels, 4 TDMs
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4 SCCs, 2 SMCs, SPI, I2C
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Memory controller built from SDRAM, UPM, GPCM machines
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New features -- USB, RMII