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MPC8321EVRAFDC

厂商：
Freescale
类别：
PowerQUICC II pro
包装：
Tray
封装：
PBGA-PGE 516 27SQ1.25P1
无铅情况/ROHS：
无铅
描述：
8321 NOPB PBGA W/ ENCR

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  • 参数
  • 描述
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参数 数值
速度 333MHz
处理器类型 MPC83xx PowerQUICC II Pro 32-Bit
电压 1V
安装类型 Surface Mount
Co Processor Type QUICC
External Memory Supported SDRAM / FLASH / EPROM / DRAM / DDR2 / DDR1
RoHS Certificate of Analysis (CoA) Contact Us
External Bus Interface Local / PCI
Package Thickness (nominal) (mm) 2.250
Pin/Lead/Ball Count 516
Power Dissipation (Typ) (W) 1.8
Core: Operating Frequency Max (Max) (MHz) 333
Export Control Classification Number (US) 5A002
Status Active
Maximum Time at Peak Temperature (s) 40
Minimum Package Quantity (MPQ) 40
Core: Type e300
Package Material Plastic
Description 8321 NOPB PBGA W/ ENCR
Core: Performance in MIPS 633
Device Weight (g) 4.37440
Harmonized Tariff (US) Disclaimer 8542.31.0000
Material Composition Declaration (MCD) Download MCD Report Download MCD Report
MPQ Container TRAY
Power Dissipation (Max) (W) 2
Tape & Reel No
UL94 (plastics flammability test) V0: burning stops within 10 seconds on a vertical specimen; no drips allowed
Budgetary Price($US) 1000 @ $15.89 each
Package Description and Mechanical Drawing PBGA-PGE 516 27SQ1.25P1
REACH SVHC Freescale REACH Statement
Part Number MPC8321EVRAFDC
Co Processor Frequency (Max) (MHz) 200
Core: Operating Voltage (Spec) (V) 1
Junction Operating Temperature (Max) (°C) 105
Life Cycle Description (code) PRODUCT RAPID GROWTH
Application/Qualification Tier COMMERCIAL, INDUSTRIAL
Moisture Sensitivity Level (MSL) 3
USB USB 2.0
Mounting Style Surface Mount
Preferred Order Quantity (POQ) 200
Cache (kByte) 32
POQ Container BOX
2nd Level Interconnect e1
Ambient Operating Temperature (Min-Max) (°C) 0 to 105
Number of Reflow Cycles 3
Peak Package Body Temperature (PPT)(°C) 260
Material Type Tested Packaged Device
Micron Size (μm) .09
Package Length (nominal) (mm) 27.000
Package Width (nominal) (mm) 27.000
Leadtime (weeks) 8
Sample Exception Availability Y
Ethernet 100 BaseT
Floor Life 168 HOURS
Halogen Free Yes
I/O Operating Voltage (Max) (V) 1.8 / 3.3

The MPC8321E PowerQUICC™ II Pro is a member of the MPC8323E family of cost-effective network communications processosr that meet the requirements of several small office/home office (SOHO), access, IP services and industrial control applications. It provides better CPU performance, additional functionality and faster interfaces than current PowerQUICC™ II processors while addressing important time to market, price, power consumption and board real estate requirements

Core Complex
The MPC8321E incorporates a unique configuration of the e300c2 (MPC603e-based) core. While this version of e300 core does not have a Floating-Point Unit (FPU) it has been designed to include dual integer units as well as a modified multiply instruction. These architectural enhancements enable more efficient operations to be executed in parallel, resulting in significant performance improvement. The core also includes 16 Kbytes of L1 instruction and data caches and on-chip memory management units (MMUs). The MPC8321E also includes a 32-bit PCI controller, four DMA channels, a flexible local bus, and a 32-bit DDR-1/DDR-2 SDRAM memory controller..

QUICC Engine™ Technology
A new single-RISC version of the QUICC Engine™ communications engine forms the heart of the networking capability of the MPC8321E. The QUICC Engine block contains several peripheral controllers and a single 32-bit reduced instruction set computing (RISC) controller. Unique microcode packages provide support for NAT, Firewall, IPSec, and Advanced Quality of Service (QoS). Protocol support is provided by the main workhorses of the device - the unified communication controllers (UCCs). Each of the five UCCs can support a variety of communication protocols:

  •  Up to (3) 10/100 Mbps Ethernet
  •  High-level data link control (HDLC)
  •  Up to (4) Time division multiplexing (TDM)
  •  Binary synchronous communications protocol (BISYNC)
  •  UCC can also support USB 2.0 (full/low speed)

Hardware Security Engine
The security engine (SEC 2.2) on the MPC8321E allows CPU-intensive cryptographic operations to be off-loaded from the main CPU core. The security-processing accelerator provides hardware acceleration for DES, 3DES, Advanced Encryption Standard (AES), Secure Hash Algorithm (SHA)-1 and MD-5 algorithms.

System Interface Unit
The MPC8321E family also includes a 32-bit double data rate (DDR)-1/DDR/2 memory controller, a 32-bit peripheral component interconnect (PCI) controller, a 16-bit local bus and four direct memory access (DMA) channels.

Typical Applications

  •  Residential gateways
  •  SOHO networking
  •  VPN routers
  •  Access points
  •  DSLAM line cards
  •  Industrial control
  •  Test and measurement equipment
View Block Diagram

Features

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