特点
Quad 12-Bit DAC
Buffered True Rail-to-Rail Voltage Output
Maximum DNL Error: 0.5LSB
5V Operation, I
CC
: 1.1mA Typ (LTC1458)
3V Operation, I
CC
: 800μA Typ (LTC1458L)
Internal or External Reference Operation
Settling Time: 14μs to ±0.5LSB
Schmitt Trigger On Clock Input Allows Direct Optocoupler Interface
Power-On Reset and CLR Pin
SSOP-28 Package
3-Wire Cascadable Serial Interface with 250kHz Update Rate
Low Cost
典型应用
典型应用
描述
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