The Freescale MSC8103 Integrated Digital Signal Processor (DSP) is based on the SC140 DSP core. This versatile chip integrates on a single device the high-performance StarCore 140 (SC140) four-ALU (Arithmetic Logic Unit) DSP core along with 512 KB of on-chip memory, a Communications Processor Module (CPM), a 64-bit 60x-compatible system bus, a flexible System Integration Unit (SIU), and a 16-channel DMA engine. With its four ALU core, the MSC8103 can execute up to four multiply-accumulate (MAC) operations in a single clock cycle. The MSC8103 CPM is a 32-bit RISC-based communications protocol engine that can network to Time-Division Multiplexed (TDM) highways, Ethernet, and Asynchronous Transfer mode (ATM) backbones. The MSC8103 60x-compatible bus interface facilitates its connection to multi-master system architectures. The large on-chip memory, 512 KB, reduces the need for off-chip program and data memories. The MSC8103 device offers 1200 MMACS performance using an internal 300 MHz clock with a 1.6 V core and independent 3.3 V input/output (I/O).
The MSC8103 device is very similar to the MSC8101; the MSC8101 documentation listed on this page will be helpful to MSC8103 developers. The MSC8103 device uses the MSC8101 tools listed on this page.
Target Applications The MSC8103 device targets applications requiring very high performance, very large amounts of on-chip memory, and such networking capabilities as:
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Third-generation wideband wireless infrastructure systems
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IP Telephony systems
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Multi-channel modem banks
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Multi-channel xDSL
Development Tools NOTE: For information on the compiler, linker, assembler tools that have been developed for StarCore products, click on "Related Links" and visit the vendor site.
Design Tools NOTE: A library of software modules and MSC8101 device driver examples is available to accelerate bringing MSC8103 products to market.
View Block Diagram
Features
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Architecture optimized for efficient C/C++ code compilation
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Four 16-bit ALUs and two 32-bit AGUs
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1200 MMACS, running at 300 MHz
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Very low power dissipation
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Variable-Length Execution Set (VLES) execution model
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JTAG/Enhanced OnCE debug port
150 MHz Communications Processor Module (CPM)
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Programmable protocol machine using a 32-bit RISC engine
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155 Mbps ATM interface (including AAL 0/1/2/5)
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10/100 Mbit Ethernet interface
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Up to four E1/T1 interfaces, one E3/T3 interface and one E1/T1 interface
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HDLC support up to T3 rates, or 256 channels
100 MHz 64- or 32-bit wide 60x-compatible Bus interface
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Support for bursts for high efficiency
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Glueless interface to the 60x-compatible bus systems
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Multi-master support
Programmable Memory Controller
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Control for up to eight banks of external memory
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User programmable machines (UPM) allowing glueless interface to various memory types - SRAM, DRAM, EPROM, FLASH, and other user-definable peripherals
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Dedicated pipelined SDRAM memory interface
Large On-chip SRAM
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256K 16-bit words (512K Bytes)
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Unified program and data space configurable by the application
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Word and byte addressable
DMA controller
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16 DMA channels, FIFO based, with burst capabilities
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Sophisticated addressing capabilities
Small foot print package
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17 mm x 17 mm lidded FC-PBGA lead-bearing or lead-free package
Very lo