The MSC8154 device is one of Freescale's fourth-generation high-end multicore DSP devices that target the broadband wireless base stations and other communications infrastructure. The MSC8154 is a four-core DSP based on Freescale’s SC3850 StarCore technology designed to advance the capabilities of wireless broadband equipment. It delivers industry-leading performance and power savings, leveraging 45 nm process technology in a highly integrated system-on-chip (SoC) to provide performance equivalent to a 4 GHz single-core device. The MSC8154 helps equipment manufacturers and carriers create solutions and services that enable near-term, mainstream adoption of next-generation wireless standards such as 3G-LTE, WiMAX, HSPA+ and TDD-LTE. The device is designed to lower system costs by integrating functionality into a single device that previously required multiple discrete parts.
The MSC8154 DSP delivers a high level of performance and integration, combining four fully programmable new and enhanced SC3850 DSP cores, each running at up to 1 GHz with an architecture highly optimized for wireless infrastructure applications. Developed by Freescale and integrated on-chip, the MAPLE-B baseband accelerator supports hardware acceleration for Turbo and Viterbi channel decoding and for DFT/iDFT and FFT/iFFT algorithms and includes CRC processing. An internal RISC-based QUICC Engine subsystem supports multiple networking protocols to guarantee reliable data transport over packet networks while significantly offloading processing from the DSP cores.
The MSC8154 embeds large internal memory and supports a variety of advanced, high-speed interface types, including two RapidIO® interfaces, two gigabit Ethernet interfaces for network communications, a PCI Express® controller, two DDR controllers for high-speed, industry standard memory interface and four multi-channel time division multiplexing (TDM) interfaces. The MSC8154 is pin compatible with the MSC8156.
Features
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Four StarCore DSP SC3850 core subsystems operating at up to 1 GHz/8000 MMACS per core and up to 32000 MMACS per device.
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Multi accelerator platform engine for baseband (MAPLE-B)
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High-speed, high-bandwidth CLASS fabric arbitrates between the DSP cores and other CLASS masters to M2 memory, M3 memory, DDR controllers, MAPLE-B and the configuration registers
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Two DDR controllers with up to 400 MHz clock (800 MHz data) rate and 32/64-bit DDR2/3 SDRAM data bus
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32-channel DMA controller
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Dual RISC core QUICC Engine subsystem operating at up to 500 MHz
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HSSI that supports two 4x SerDes ports
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Four TDM interfaces
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UART and I⊃2;C interfaces
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Eight software watchdog timers
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Sixteen 16-bit timers and two 32-bit general purpose timers per core for RTOS support.
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I/O interrupt concentrator and virtual interrupt support, eight hardware semaphores
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Thirty-two GPIO ports multiplexed with interface signals and IRQ inputs
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Boot options: Ethernet, Serial RapidIO, I⊃2;C and serial peripheral interface (SPI)
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Three input clocks and five PLLs
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JTAG Test Access Port (TAP) and boundary scan architecture designed to comply with IEEE® Std. 1149.1™ profiling and performance monitoring support
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Reduced power dissipation with wait, stop and power down low-power standby modes
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Optimized power management circuitry
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CMOS 45 nm SOI technology in 29 mm x 29 mm, 783 ball FC-PBGA package
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This product is included in Freescale’s , with assured supply for a minimum of 10 years after launch