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LT1228CS8#TR

厂商:
Linear
类别:
电流反馈放大器
包装:
-
封装:
SO
无铅情况/ROHS:
-
描述:
100MHz Current Feedback Amplifier...

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  • 参数
  • 描述
  • 文档
参数 数值
Channels (#) 1
GBW (MHz) 100
SR (V/us) 500 (300)
Is (mA) 9 (15)
Enoise Density (nV/rtHz) 20
Single Supply (yes/no) no
Rail-to-Rail Out (yes/no) no
Packages DIP-8,SO-8
Vos (mV) 0.5
Vos TC (uV/C) 10
Inoise (pA/rtHz) 1.4
Ibias (uA) 0.4
Iout (mA) 65
Avol (V/mV)
Type CFA
Vs Min (V) 4
Vs Max (V) 36
Shutdown (yes/no) no
Rail-to-Rail In (yes/no) no
Over-the-Top (yes/no) no
CMRR (dB) 69
PSRR (dB) 80
Ts (0.1%) (ns) 45
Voh (from V+) (V) 0.8
Vol (from V-) (V) 0.8
VinCM High (from V+) (V) 1
VinCM Low (from V-) (V) 1
Av Min Stable (V/V) 1
Av Min (V/V)
Av Max (V/V)
Gain Accuracy (%)
Gain Drift (ppm/C)
Cload (pF) 2000
Comments CFA with gain control
Temp Range C
Featured no
Date Added 1984-01-01
Price 1k * $3.75 (LT1228CN8)
New no

Description
W9464G6JH is a 64M DDR SDRAM and speed involving -4 / -5 and -5I Status: Mass Production
Features
2.5V ±0.2V Power Supply for DDR400
2.4V~2.7V Power Supply for DDR500
Up to 250 MHz Clock Frequency
Double Data Rate architecture; two data transfers per clock cycle
Differential clock inputs (CLK and /CLK)
DQS is edge-aligned with data for Read; center-aligned with data for Write
CAS Latency: 2, 2.5, 3 and 4
Burst Length: 2, 4 and 8
Auto Refresh and Self Refresh
Precharged Power Down and Active Power Down
Write Data Mask
Write Latency = 1
15.6μS refresh interval (4K/64 mS Refresh)
Maximum burst refresh cycle: 8
Interface: SSTL_2

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LT1228CS8#TRPDF下载 点击下载 点击下载 Voltage Output DACs
数据表 (英文)
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LT1228CS8#TRPDF下载 点击下载 点击下载 LTC2630 - Single 12-/10-/8-Bit Rail-to-Rail DACs with Integrated Reference in SC70
设计要点 (英文)
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LT1228CS8#TRPDF下载 点击下载 点击下载 DN448 - 12-bit DAC in TSOT-23 Includes Bidirectional REF Pin for Connection to Op Amp or External High Precision Reference
产品新闻发布 (中文)
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LT1228CS8#TRPDF下载 点击下载 点击下载 LTC2630 - 采用纤巧 SC70 封装的 12 位/10 位/8 位电压输出 DAC 系列集成了内部基准
可靠性数据
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LT1228CS8#TRPDF下载 点击下载 点击下载 R461 Reliability Data