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LT1014IN

厂商:
Linear
类别:
低功率放大器
包装:
-
封装:
PDIP
无铅情况/ROHS:
-
描述:
四通道精准运算放大器

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  • 参数
  • 描述
  • 文档
参数 数值
Inoise (pA/rtHz) 0.07
Vs Max (V) 44
New no
Ibias (nA) 12 (20)
Enoise Density (nV/rtHz) 22
Temp Range C,I
Vos TC (uV/C) 0.3 (2)
VinCM Low (from V-) (V) -0.3
Channels (#) 4
Avol (V/mV) 8000
Single Supply (yes/no) yes
Av Min Stable (V/V) 1
Cload (pF) 100
Rail-to-Rail Out (yes/no) no
Over-the-Top (yes/no) no
Iout (mA) 25
LF Enoise (uVpp) 0.55
Shutdown (yes/no) no
Featured no
Rail-to-Rail In (yes/no) no
Type VFB
CMRR (dB) 117
Vos (uV) 40 (150)
PSRR (dB) 120
Vs Min (V) 4
Vol (from V-) (V) 1
Ts (0.1%) (ns)
Av Min (V/V)
Is (mA) 0.35 (0.5)
Packages DIP-14, SOW-16
GBW (MHz) 0.8
SR (V/us) 0.4
Voh (from V+) (V) 1
VinCM High (from V+) (V) 1.2
Av Max (V/V)
Gain Accuracy (%)
Gain Drift (ppm/C)
Comments Single supply precision op amp
Date Added 1984-01-01
Price 1k * $3.45 (LT1014DN)

Designed for engine management, the Qorivva MPC5553 32-bit embedded controller is the first device from Freescale's Qorivva MPC55xx family to offer an on-chip fast Ethernet controller (FEC). Containing the Power Architecture® core, the Qorivva MPC5553 is ideal for any application that requires complex, real-time control and can conveniently be networked with the rest of the world. It offers system performance of up to five times that of its MPC500 predecessors, while bringing you the reliability and familiarity of the proven Power Architecture technology.


Features


Freescale's e200z6 Core
  • High-performance 132 MHz 32-bit Power Architecture core
  • Memory management unit (MMU) with 32-entry fully associative translation lookaside buffer (TLB)
  • SPE (signal processing extension): DSP, SIMD and floating point capabilities

Memory
  • 1.5 MB of embedded flash memory with error correction coding (ECC) and read while write capability (RWW)
  • 64 KB on-chip static RAM with ECC
  • 8 KB of cache (with line-locking) that can be configured as additional RAM

System
  • An enhanced time processor unit (eTPUs) with 32 I/O channels and 14.5 KB of dedicated SRAM
  • 32-channel eDMA (enhanced direct memory access) controller
  • Interrupt controller (INTC) capable of handling 210 selectable-priority interrupt sources
  • Frequency modulated phase-locked loop (FMPLL) to assist in electromagnetic interference (EMI) management
  • MPC500 compatible external bus interface
  • Nexus IEEE®-ISTO 5001 class 3+ multicore debug capabilities > 5/3.3V IO, 5V ADC, 3.3V/1.8V bus, 1.5V core
  • Fast Ethernet connection(FEC)
  • 416-pin PBGA, 324-pin PBGA, or 208 MAPBGA package
  • Temperature range: -40 to 125ºC

I/O
  • 40-channel dual enhanced queued analog-to-digital converter (eQADC)—up to 12 bit resolution and up to 1.25us conversions, six queues with triggering and DMA support
  • Three deserial serial peripheral interface (DSPI) modules—16-bits wide up to six chip selects each
  • Two controller area network (CAN) modules with 64 buffers each
  • Two enhanced serial communication interface (eSCI) modules
  • 24-channel enhanced multiple I/O system (EMIOS) with unified channels

Development Tools
  • A comprehensive suite of hardware and software development tools is available to help simplify and speed system design
  • Development support is available from leading tools vendors providing compilers, debuggers and simulation development environments

Included in Freescale’s product longevity program
  • product longevity program with assured supply for a minimum of 15 years after launch

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