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AV31221161

厂商：
Panasonic
类别：
微动开关
包装：
-
封装：
-
无铅情况/ROHS：
无铅
描述：
FS型

我要询价我要收藏

  • 参数
  • 描述
参数 数值
额定 0.1A 125V AC/0.1A 250V AC/0.1A 30V DC
特点 Consistent quality and high precision through sophisticated automatic fabrication system. Low-level circuit types available. Long life version available.
接触形式 SPDT
电气寿命 2x10^5
订货产品号 AV31221161
激励器 Hinge lever
国外标准 -
OF 0.16N
保护构造 IP40
摆杆安装位置 Forward
端子形状 Solder terminal with guard
标准・寿命 Standard
触点材料 Gold-clad triple layer

The MPC8241 Integrated Host Processor fits applications where cost, space, power consumption and performance are critical requirements. This device provides a high level of integration, reducing chip count from five discrete chips to one, thereby significantly reducing system component cost. High integration results in a simplified board design, less power consumption and a faster-time-to-market solution. This cost-effective, general purpose integrated processor targets systems using PCI interfaces in networking infrastructure, telecommunications, and other embedded markets. It can be used for control processing in applications such as routers, switches, network storage applications and image display systems.


Features

  • 166-266 MHz RISC processor core
  • 32-bit PCI interface operating at up to 66 MHz
  • Memory controller offering SDRAM support up to 133 MHz operation, support up to 2 GB
  • General Purpose I/O and ROM Interface Support
  • Two-channel DMA controller that supports chaining
  • Messaging unit with I2O messaging support capability
  • Industry-standard I2C interface
  • Programmable interrupt controller with multiple timers and counters
  • 16550 compatible DUART
  • Wireless LAN
  • Routers/Switches
  • Multi-channel modems
  • Network storage
  • Image display systems
  • Enterprise I/O processor
  • Internet access device (IAD)
  • Disk controller for RAID systems
  • Copier/printer board control
  • Embedded Computing
  • MPC603e processor core
    • High-performance, superscalar processor core built on Power Architecture technology
    • Floating-point unit, integer, load/store, system register and branch processing unit
    • 16K instruction cache, 16K data cache
    • Lockable portion of L1 cache
    • Dynamic power management
    • Software-compatible with processors built on Power Architecture technology
  • Memory interface
    • 133 MHz memory bus capability
    • Programmable timing EDO DRAM or SDRAM
    • High-bandwidth bus (32/64-bit data bus) to DRAM
    • Supports one to eight banks of 16-, 64-, 128, 256 or 512Mbit DRAM
    • Supports 1 Mbyte to 2 Gbyte DRAM memory
    • Contiguous memory mapping
    • 272 Mbytes of ROM space
    • 8-bit, 16-bit, 32-bit, or 64-bit ROM
    • Supports bus-width writes to flash
    • Read-modify-write parity support (selectable)
    • ECC support (selectable)
    • SDRAM, DRAM buffer data-path
    • Error injection/capture on data path
    • LVTTL compatible
    • PortX: 8-, 16-, 32- or 64-bit general-purpose I/O port uses ROM controller interface with address strobe
  • 32-bit PCI interface operating up to 66 MHz
    • PCI 2.2 compatible
    • PCI 5.0 V tolerant
    • Support for PCI locked accesses to memory
    • Support for accesses to all PCI address spaces
    • Selectable big- or little-endian operation
    • Store gathering of processor-to-PCI writes and PCI-to-memory writes
    • Memory prefetching of PCI read accesses
    • Parity support (selectable)
    • Selectable hardware-enfo

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