The 68376 is a highly-integrated 32 bit microcontroller that combines high-performance data manipulation capabilities with powerful peripheral subsystems.This MCU is built up from standard modules that interface through a common intermodule bus (IMB).
The MCU incorporates a 32 bit CPU (CPU32), a System Integration Module (SIM), a Time Processing Unit (TPU), a Queued Serial Module (QSM), a 3.5 Kbyte TPU Emulation RAM Module (TPURAM), a Configurable Timer Module 4 (CTM4), a 10 bit Queued Analog-to-Digital Converter Module (QADC), a 4 Kbyte Static RAM Module (SRAM), a CAN 2.0B Protocol Module (TouCAN™) and a 8 Kbyte Masked ROM (MRM).
Features
-
32 Bit Archirecture
-
Virtual Memory Implementation
-
Table Lookup and Interpolate Instruction
-
Improved Exception Handling for Controller Applications
-
High Level Language Support
-
Background Debugging Mode
-
Fully Static Operation
-
External Bus Support
-
Programmable Chip Select Outputs
-
System Protection Logic
-
Watchdog Timer, Clock Monitor and Bus Monitor
-
Two 8 bit Dual Function Input/Output Ports
-
One 7 bit Dual Function Output Port
-
Phase-Locked Loop (PLL) Clock System
-
Dedicated Micro-Engine Operating Independently of CPU32
-
16 Independent Programmable Channels and Pins
-
Each Channel has an /Event Register Consisting of a 16 bit Capture Register, a 16 Bit
-
Compare Register and a 16 Bit Comparator
-
Any Channel can Perform Any Time Function
-
Each Channel has Six or Eight 16 Bit Parameter Registers
-
Each Timer FunctionMay Be Assigned to More Than One Channel
-
Two Timer Counter Registers with Programmable Prescalers
-
Each Channel Can Be Synchronized to Either or Both Counters
-
Selectable Channel Priority Levels
-
Two 16 bit modulus counters (MCSM)
-
16 Bit Free-Running Counter (FCSM)
-
4 Double-action capture/compare channels, with PWM mode (DASM)
-
4 Dedicated PWM channels, each having its own 16 bit modulus counter (PWMSM)
-
Enhanced serial communication interface (SCI)
-
Modulus baud rate generator
-
Parity detection
-
Queued serial peripheral interface (QSPI)
-
80 byte static RAM to perform queued operations
-
Up to 16 automatic transfers
-
Continuous cycling, 8 to 16 bits per transfer, LSB or MSB first
-
Dual function I/O pins
-
16 Channels internally; up to 41 directly accessible channels with external multiplexing
-
Six automatic channel selection and conversion modes
-
Two channel scan queues of veriable length, each with a variable number of sub-queues
-
40 Result registers and three result alignment formats
-
Programmable input sample time
-
Direct control of multiplexers
-
Full implementation of CAN protocol specification, version 2.0 A and B
-
16 receive/transmit message buffers of 0 to 8 bytes data length
-
Global mask register for message buffers 0 to 13
-
Independent mask registers for message buffers 14 and 15
-
Programmable transmit first scheme: lowest ID or lowest buffer number
-
16 bit free-running timer for message time-stamping
-
Low power slee